One of the critical aspects of a memory is the signal path from a selected memory cell to the output. The memory cell produces a relatively small signal to indicate a particular logic state which comprises one bit of information. This small signal is amplified through a number of stages and finally output as a relatively strong output signal. The strength of the signal primarily relates to voltage level and current drive capability. The signal from the memory cell is generally weak in both voltage and current drive, and thus the need for amplification. This amplification is necessary, but the amplification path is also a critical path in determining the speed with which the memory can operate. Thus, it is desirable to perform the needed amplification as quickly as possible. Generally, there is a speed/power tradeoff. Thus, the speed of amplification for a particular circuit type can be increased but at the cost of using more power. There are two major components of power usage, standby and active. The active power tends to increase as the frequency increases. Thus, at some maximum frequency of operation, the memory is using maximum power for a given power supply voltage. The maximum power that can be consumed is a function of how well heat can be dissipated. If the heat becomes too great, the memory can experience various problems including actually permanently damaging the particular memory device. Thus, it is desirable to save power whenever it is feasible, especially if it can be done without degrading the performance of the memory device.
The amplification stage, particularly at high frequency, is a major contributor to the overall power consumed by the device. This is due to a large extent because speed of amplification is so important. There are power saving techniques available but they generally have only nominal affect at the higher frequencies of operation. One such technique is to power down the amplifier stage some predetermined time after an address transition. Another approach has been to power-up the sense amplifier stage with a transition signal initiated by an address transition, detect when the output is valid, and disable the transition signal in response to detecting that the output is valid. This is described in "Two Novel Power-Down Circuits on the 1 Mb CMOS SRAM," by Masataka Matsui, et al., in the 1988 Symposium On VLSI Circuits, Digest of Technical Papers, Circuits Symposium, Tokyo, IEEE Cat. No. 88 Th 0227-9, pages 55 and 56. This approach continues to offer power-savings benefits even at higher frequencies. There are, however, some problems with this approach. One problem is that the data can give a false reading of validity. The point in the amplification stage at which the validity is detected may have a voltage movement which is sufficient to cause the validity detector to falsely detect that the data is valid. This can happen due to noise in the system which is amplified or to unbalanced bit lines which begin with a differential which opposite to that which will be eventually established for valid data. If the detector falsely detects that the data is valid, the sense amplifier will be disabled prematurely.